(a) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a synchronous semiconductor memory device capable of operating in synchrony with an external clock signal.
(b) Description of the Related Art
Recently, there is an increasing request that the semiconductor memory device be improved to comply with enhanced CPU performance such as a high-speed operation. However, due to physical limitation for miniaturization of constituent elements or an increase of the integration scale in the semiconductor memory device, this request has not yet been effectively solved. Some of the solutions responding to the request are proposed for synchronous semiconductor memory devices in Patent Publications JP-A-61(1986)-148692, JP-A-6(1994)76566, JP-A-8(1996)-96573 etc.
FIG. 1 is a block diagram of an example of such proposals for the synchronous semiconductor memory devices, which comprises: an address input circuit 101 connected to a plurality of address input terminals ADD; a plurality of control signal input circuits 102, 103, 104 and 105 connected to control signal input terminals RASB, CASB, WEB and CSB, respectively; a clock input circuit 106 for receiving an external clock signal CLK to output a first internal clock signal .phi.1; a first synchronous signal generator 114 for receiving the first internal clock signal .phi.1 to output internal second and third clock signals .phi.2 and .phi.3; a second synchronous signal generator for receiving the first internal clock signal .phi.1 to output a fourth internal clock signal .phi.4, a command decoder 112 for receiving and decoding signals from the input circuits 101, 102, 103, 104 and 105; a latch circuit 113 for receiving outputs from the command decoder 112 to output a read control signal .phi.8 in synchrony with the second internal clock signal .phi.2; a data latch circuit 118 for receiving the read control signal .phi.8 and a fourth internal clock signal .phi.4 to output an output enable signal .phi.9; a burst counter 107 for receiving an output from the address input circuit 101 to output a plurality of internal address signals .phi.5; a column decoder 108 for receiving the internal address signals .phi.5 to output a plurality of column selection signals .phi.6; a row decoder 110 for receiving an input from the address input circuit 101 to output a row selection signal .phi.7; a memory cell array 111 including a plurality of memory cells; a plurality of sense amplifiers 109 for amplifying data signals supplied from the memory cell array 111 by responding to the column selection signals .phi.6; a plurality of latch circuits 116 for latching outputs from the corresponding sense amplifiers 109 to supply the latched data in synchrony with the third internal clock signal .phi.3; a data amplifier 117 for receiving outputs from the latch circuits 116 to output a pair of data signals D1T and D1N (D1T/D1N or D1T/N); AND gates AN1 and AN2 for receiving the pair of data D1T/D1N signals and an inverted output enable signal x.phi.9 to output a pair of data signals D2T/D2N; and an output circuit block 130 including data latch circuits for receiving the data signals D2T/D2N and the fourth internal clock signal .phi.4; and a pair of output stage transistors TR1 and TR2 for receiving a pair of data signals D3T/D3N corresponding to the data signals D2T/D2N.
In FIG. 1, other circuit elements such as buffer inverters and circuit blocks which are not important to understand the present invention are omitted.
FIG. 2 shows a practical configuration of the output circuit block 130 shown in FIG. 1 together with the synchronous generator 115, wherein the power source designated by VVT is specified as a voltage source supplying a higher voltage than the other power source. The circuit block 130 comprises data latch circuits 119 and 120 for receiving data signals D2T/D2N to control the output timing of the output transistors TR1 and TR2, a voltage converter 51 for receiving data 92 from the latch circuit 119 to output a high-level data or data having a high voltage level corresponding to the higher voltage source VVT, and a first inverter 71 for receiving the high-level data signal from the voltage converter 51 to output the data D3T having a higher voltage corresponding to the higher voltage source VVT, the data signal D3T being supplied to the output transistor TR1, and a second inverter 61 for receiving an output 97 from the data latch circuit 120 to output the data signal D3N to the output transistor TR2.
In FIG. 1, the group of the sense amplifiers 108, latch circuit 116, data amplifier 117, AND gates AN1 and AN2, latch circuits 119 and 120, voltage converter 51, inverters 71 and 61 is provided in number corresponding to the number of output pins DQ of the memory device.
Generally, the output transistors TR1 and TR2 are designed to have a larger current driving capability than other transistors in order for driving an external circuit-having a large parasitic capacitance. For driving the output transistors TR1 and TR2, buffer inverters 71, 61, 62 and 63 are provided in the latch circuits 119 and 120 and-between the latch circuit 119 and 120 and corresponding output transistor TR1 or TR2, as shown in FIG. 2.
The internal clock signal .phi.4 is generally delayed in transmission along the transmission line between the synchronous clock generator 115 provided in the vicinity of the input side of the memory device and the latch circuits 119 and 120 provided in the vicinity of the output terminal DQ, although a buffer inverter 65 is provided at the output stage of the synchronous clock generator 115 for driving the plurality of latch circuits 119, 120 etc. connected through the transmission line having a large parasitic capacitance.
The voltage converter 51 is provided on the data path for supplying a higher voltage than a normal power source voltage at a node 91 to cancel an ON-resistance of the output transistor TR1, thereby supplying a sufficient high level of the output data signal.
FIG. 3 shows a timing chart of signals in the semiconductor memory device as described above, wherein a case of "CAS latency=" during a read burst operation is exemplified. The term "CAS latency" means clock cycles necessary for supplying a read data through the output pin after an external read command is received. In the case of "CAS latency=3" three clock cycles are necessary for a read-out operation, or in other words, the read data is supplied through the output pin DQ after three clocks are counted from the receipt of the external read command.
During a first clock cycle C1 in Fig.3, an external read command is input in synchrony with the rising edge of the external clock signal CLK. Responding to the external read command, the command decoder 112 supplies an internal read command signal to a latch circuit 113 for instructing a read operation. During a next clock cycle C2, a read control signal .phi.8 from the latch circuit 113 falls to a low level in synchrony with the first internal clock signal .phi.2 for effecting a read operation, and the output enable signal .phi.9 falls to a low level in synchrony with the falling edge of the fourth internal clock signal .phi.4.
During the second clock cycle C2, the data read out from the memory cell array 111 is output from the latch circuit 116 in synchrony with the third internal clock .phi.3, and output from the data amplifier 117 as a pair of data signals D1T/D1N. After the output data enable signal .phi.9 falls to a low level during the clock cycle C2, the data signals D1T/D1N pass through AND gates AN1 and AN2, respectively, as data signals D2T/D2N, which are then supplied to the latch circuits 119 and 120. During a third clock cycle C3, the data signals D2T/D2N are supplied from the latch circuits 119 and 120 in synchrony with the fourth internal clock signal .phi.4 and delivered through the output transistors and the output pin DQ.
In general, it is requested that the access time be shorter in a semiconductor memory device. For example, synchronous semiconductor integrated circuits are controlled in synchrony with an external clock signal. The total system design for a CPU system can be made easy if a smaller clock access time is realized in the synchronous semiconductor memory device for a device receiving the data output from the semiconductor memory device. In FIG. 3, the clock access time of the synchronous semiconductor memory device is designated by t1, and a set-up time for the device receiving the data, output from the semiconductor memory device is designated by t2. That is, the clock access time t1 of the memory device should be reduced for an easy design of the CPU system.
The clock access time t1 is determined by a sum of a time interval between a rising edge of the external clock signal CLK and the corresponding rising edge of the internal clock signal .phi.4 which rises after the external clock passes through the clock input circuit 106 and the synchronous clock generator 115, and a time interval between the rising edge of the internal clock signal .phi.4 and a time instant at which the data signal is output through the output pin after the data signals pass the latch circuits 119 and 120 and drive the output transistors TR1 and TR2.
It is preferred to have less number of buffer stages and proper number of fan-outs along the clock signal path from the clock input circuit 106 to the inputs of the latch circuit receiving the internal clock signal .phi.4. However, as described before, due to a large parasitic capacitance of the clock line for the internal clock signal .phi.4, the number of fan-outs increases if the number of buffer stages is reduced, thereby retarding the transmission of the clock signal to increase the clock access time.
The voltage converter 51 in FIG. 2 especially delays the signal transmission from node 92 to node 91, generating a propagation delay for the signal at node 92 larger than, for example, the propagation delay of the signal at node 96 which does not pass the voltage converter. In short, a large clock access time results in the semiconductor memory device because of the voltage converter.
Moreover, due to a timing difference between the pair of data signals D3T/D3N, the order of the timing at which the signal at node 91 falls and the timing at which the signal at node 96 rises, which should be in this order, are reversed, causing a penetration current or pass through current flowing through both the transistors TR1 and TR2. For the protection against the pass-through current, the driving capability of the inverters 61, 62, 63 and 71 may be adjusted. However, such an adjustment sometime involves a difficulty in the design in view of process variation.